Ch7 數位電路設計

一種功能的數位系統，並不是只有一種敘述的方法，而不同的敘述方法可能會造成不同的合成、不同的效能、不同的電路，但卻是可以是相同的結果，所以這裡的範例僅提出一種方法做參考，學習的初期只需達到結果就好，等到了解後再去思考該如何做到簡單、如何不浪費邏輯資源。

7.1多工器( Multiplexier )

程式( 2 to 1 多工器 )：

module Mux2_1( In1, In2, Sel, Out );

    input   In1, In2, Sel;
    output  Out;

    wire    In1, In2, Sel;
    reg     Out;

    always @( In1, In2, Sel ) begin
        if( !Sel )
            Out <= In1;
        else
            Out <= In2;
    end

endmodule

7.2 解多工( DeMultiplexier )

程式( 1 to 2解多工)：

module DeMux2_1( In, Sel, Out1, Out2 );

    input   In, Sel;
    output  Out1, Out2;

    wire    In, Sel;
    reg     Out1, Out2;

    always @( In, Sel ) begin
        case( Sel )
            1'b0: Out1 <= In;
            1'b1: Out2 <= In;
        endcase
    end

endmodule

7.3 編碼器( Encode )

程式( 8 to 3編碼器)：

module EnCoder( In, Out );

    input   [7:0] In;
    output  [2:0] Out;

    wire    [7:0] In;
    reg        [2:0] Out;

    always @( In ) begin
        case( In )
            8'b0000_0001:   Out <= 3'b000;
            8'b0000_0010:   Out <= 3'b001;
            8'b0000_0100:   Out <= 3'b010;
            8'b0000_1000:   Out <= 3'b011;
            8'b0001_0000:   Out <= 3'b100;
            8'b0010_0000:   Out <= 3'b101;
            8'b0100_0000:   Out <= 3'b110;
            8'b1000_0000:   Out <= 3'b111;
            default:        Out <= 3'bxxx;
        endcase
    end

endmodule

7.4 解碼器( Decode )

程式( 3 to 8解碼器)：

module DeCoder( In, Out );

    input   [2:0] In;
    output  [7:0] Out;

    wire    [2:0] In;
    reg     [7:0] Out;

    always @( In ) begin
        case( In )
            3'b000:     Out <= 8'b0000_0001;
            3'b001:     Out <= 8'b0000_0010;
            3'b010:     Out <= 8'b0000_0100;
            3'b011:     Out <= 8'b0000_1000;
            3'b100:     Out <= 8'b0001_0000;
            3'b101:     Out <= 8'b0010_0000;
            3'b110:     Out <= 8'b0100_0000;
            3'b111:     Out <= 8'b1000_0000;
            default:    Out <= 8'bxxxx_xxxx;
        endcase
    end

endmodule

7.5 比較器( Comparator )

程式( 比較器 )：

module Comparator( In1, In2, Out );

    input   In1, In2;
    output  [2:0] Out;

    wire    In1, In2;
    reg     [2:0] Out;

    always @( In1, In2 ) begin
        Out[0] <= ( In1 > In2 );
        Out[1] <= ( In1 == In2 );
        Out[2] <= ( In1 < In2 );
    end

endmodule

7.6 算術邏輯運算單元( ALU )

程式( ALU )：

`define    ADD 2'b00
`define    SUB 2'b01
`define    AND 2'b10
`define    OR  2'b11

module ALU( Data_A, Data_B, OP_Code, Data_Out );

    parameter   Data_Size = 8;
    parameter   OP_Code_Size = 2;

    input   [Data_Size-1:0] Data_A, Data_B;
    input   [OP_Code_Size-1:0] OP_Code;
    output  [Data_Size-1:0] Data_Out;

    reg     [Data_Size-1:0] Data_Out;

    always @( Data_A, Data_B, OP_Code ) begin
        case( OP_Code )
            `ADD:       Data_Out <= Data_A + Data_B;
            `SUB:       Data_Out <= Data_A - Data_B;
            `AND:       Data_Out <= Data_A & Data_B;
            `OR:        Data_Out <= Data_A | Data_B;
            default:    Data_Out <= 0;
        endcase
    end

endmodule

7.7 上數計數器( Counter )

程式( 計數器 )：

module Counter( CLK, RST, Cnt_Num, Cnt_Data );

    parameter Cnt_Num_Size = 2;
    parameter Cnt_Data_Size = 16;

    input   CLK, RST;
    input   [Cnt_Num_Size-1:0] Cnt_Num;
    output  [Cnt_Data_Size-1:0] Cnt_Data;

    wire    CLK, RST;
    wire    [Cnt_Num_Size-1:0] Cnt_Num;
    reg     [Cnt_Data_Size-1:0] Cnt_Data;

    always @( posedge CLK, negedge RST ) begin
        if( !RST )
            Cnt_Data <= 0;
        else
            Cnt_Data <= Cnt_Data + Cnt_Num;
    end

endmodule

7.8 有限狀態機( Finite State Machine )

程式( FSM )：

module Finite_State_Machine( CLK, RST, State );

    parameter   State_A = 2'b00, State_B = 2'b01,
                State_C = 2'b10, State_D = 2'b11;

    input   CLK, RST;
    output  [1:0] State;
    reg     [1:0] State;

    always @( posedge CLK, negedge RST ) begin
        if( !RST )
            State = State_A;
        else
            case( rState )
                State_A:    State <= State_B;
                State_B:    State <= State_D;
                State_C:    State <= State_A;
                State_D:    State <= State_C;
                default:    State <= State_A;
            endcase
    end

endmodule